I'd give them another look. Yet, I am concerned about the footprint and circuit traces used by parts under EAR restriction. I'd not want to get in trouble if the schematic design and Gerber file are under EAR restriction - I had to do a paperwork rather recently on a few parts, including the processor I picked for this oscilloscope.
EDITED:
paul1598419, yup - that's why I have to be careful with my options. 100 MHz may be nothing to sneeze at, however what I am worried about is the harmonics since the FPGA I will be using to handle the capture have to collect everything and submit to the Cortex M7 CPU or if I wanna a bit more kicks, Texas Instruments C67x VLIW DSP - which can then show up in the screen as suprious harmonics noises. It is hard to filter that noises out unless I can use software FFT filtering which tend to cost a lot of CPU time. So, I have to use hardware and software filtering somehow to reduce CPU usage so it can stay focused on ADC signal capture and measurement.
